1. Field of the Invention
Generally, the present specification relates to the field of integrated circuits and, more particularly, to the formation of sidewall spacers adjacent gate electrodes of transistors.
2. Description of the Related Art
Integrated circuits typically include a large number of circuit elements, which include, in particular, field effect transistors. In a field effect transistor, a gate electrode may be separated from a channel region by a gate insulation layer that provides electrical insulation between the gate electrode and the channel region. Adjacent the channel region, a source region and a drain region are provided.
The channel region, the source region and the drain region are formed in a semiconductor material, wherein the doping of the channel region is different from the doping of the source region and the drain region. Depending on an electric voltage applied to the gate electrode, the field effect transistor may be switched between an on-state and an off-state.
For forming the source region and the drain region, one or more ion implantation processes including an irradiation with ions of a dopant material may be employed. The ion implantation processes may be performed after the formation of the gate insulation layer and the gate electrode. The gate electrode may absorb ions impinging thereon, so that substantially no ions or only a small amount of ions is implanted into the channel region below the gate electrode. Ions impinging on portions of the semiconductor material adjacent the gate electrode are included into the semiconductor material and provide the doping of the source region and the drain region.
For reducing short channel effects in field effect transistors, relatively complex dopant profiles including a source extension and a drain extension adjacent the channel region may be provided in the source region and the drain region. For providing a desired dopant profile, one or more sidewall spacers may be formed adjacent the gate electrode of a field effect transistor.
In some examples of field effect transistors, a first sidewall spacer of a first electrically insulating material, for example silicon dioxide, may be formed directly adjacent the gate electrode. After the formation of the first sidewall spacer, a first ion implantation process may be performed for forming the source extension and the drain extension.
Thereafter, a second sidewall spacer of a second electrically insulating material, for example silicon nitride, may be formed adjacent the first sidewall spacer and a second ion implantation process may be performed for forming portions of the source region and the drain region other than the source extension and the drain extension. An ion energy used in the second ion implantation process may be greater than an ion energy used in the first ion implantation process, so that portions of the source region and the drain region other than the source and drain extensions have a greater depth.
For forming a sidewall spacer adjacent a gate electrode, a layer of a spacer material from which the sidewall spacer is to be formed may be deposited. Thereafter, an anisotropic etch process may be performed. In the anisotropic etch process, portions of the layer of spacer material over substantially horizontal portions of the semiconductor structure, such as, for example, portions adjacent the gate electrode, are removed at a greater etch rate than portions of the layer of spacer material at the sidewalls of the gate electrode, so that portions at the sidewalls of the gate electrode can remain and form the sidewall spacer. For depositing the layer of spacer material, deposition processes such as, for example, plasma enhanced chemical vapor deposition may be employed. The anisotropic etch process may be a dry etch process.
Using plasma enhanced chemical vapor deposition for depositing a layer of spacer material, such as silicon nitride, may have issues associated therewith when small field effect transistors, for example, field effect transistors of technology nodes smaller than the 45 nm technology node, such as the 28 nm node, are formed.
In particular, the thickness of a silicon nitride layer deposited by plasma enhanced chemical vapor deposition may depend on the pitch between adjacent transistor devices. In transistors of the 28 nm technology node, for instance, a thickness difference between portions of a silicon nitride layer formed on single pitch field effect transistors and portions of the silicon nitride layer formed on double pitch field effect transistors, may be on the order of magnitude of about 20%.
This can lead to substantial differences of device characteristics between single pitch field effect transistors and double pitch field effect transistors, which can adversely affect the yield of a process for manufacturing a semiconductor structure. For addressing such issues, special processes for depositing a highly conformal layer from which sidewall spacers may be formed, in particular for depositing a silicon nitride layer, have been proposed. Such processes may include atomic layer deposition (ALD) and in situ radical assisted deposition (iRAD).
Processes such as atomic layer deposition and in situ radical assisted deposition may help to obtain a better conformity of a layer of spacer material, in particular of a silicon nitride layer, so that smaller thickness differences between portions of the layer on single pitch field effect transistors and portions on double pitch field effect transistors may be obtained.
However, the use of highly conformal silicon nitride layers for the formation of sidewall spacers may adversely affect the performance of P-channel transistors. For a given leakage current in the off-state, P-channel transistors including a silicon nitride sidewall spacer that has been formed from a silicon nitride layer deposited by conventional plasma enhanced chemical vapor deposition may have a substantially greater current in the on-state than a P-channel transistor including a silicon nitride sidewall spacer that has been formed from a silicon nitride layer deposited by means of in situ radical assisted deposition. A performance degradation of up to 10% has been observed in P-channel field effect transistors including a silicon nitride sidewall spacer formed from a silicon nitride layer that has been deposited by means of in situ radical assisted deposition.
The present disclosure provides manufacturing processes wherein the above-mentioned issue may be avoided or at least reduced.